This invention relates to partial wafer processing and more particularly to processing multiple random size wafers in pick and place equipment for operations using a wafer map.
A typical semiconductor wafer 100 containing a plurality of dies and having an orientation marker 102 (e.g., in the form of a flat edge, a wafer flat, a wafer notch, or similar other) is illustrated in FIG. 1, according to prior art. An inkless assembly process uses an electronic wafer map instead of ink to describe die attributes such as quality, and position. The quality may be expressed as a single bit value, e.g., good or bad, accept or reject, or multiple bit value such as good first grade, and good second grade. The wafer map includes data and/or information that provides an exact location and test results for each die on the wafer. The exact location for each die is determined by using a wafer map coordinate system set up with reference to a reference die 112 located at origin (0,0). A mirror area 106 may be used to determine the location of the reference die 112. The accept-reject function of a pick-and-place system is driven by the wafer map instead of being controlled by an optical detector to detect a presence of the ink. Thus, the inkless assembly process based on the wafer map eliminates the need for inking a reject die at a wafer fabrication facility by using the wafer map data available from a probe tester to position the wafer to the exact location of all the good dies on pick-and-place systems such as a die bonder or tape and reel. Direct positioning on the good dies is possible without scanning the entire wafer.
The wafer map data includes a plurality of bin numbers to categorize the attributes and/or properties of each one of the dies. For example, bin 1 may include all good first grade dies, bin 2 may include all good second grade dies, bin 3 may include all plug dies, bin 4 may include all bad edge dies, and bin 5 may include edge bad dies. Each die may be placed in a particular bin based on the results of the probe testing. A full wafer such as the wafer 100 has one reference die such as the reference die 112. Wafers may be processed as a full wafer and/or as a partial wafer such as halves illustrated in FIG. 2, quarters illustrated in FIG. 3, and/or any portion of the full wafer as illustrated in FIG. 4, according to prior art, to match production lot size at an Assembly/Test (A/T) facility including a partial wafer processor. In case of partial wafers, reference die for each piece of the wafer is generally not available. Without a method to process partial wafers using wafer map, small die wafer map operation is incomplete and cannot be fully implemented in assembly operations. Alternatives like scrapping partial wafers or processing all dies on partial wafers are not cost effective solutions.
However, traditional tools and methods for assembly and fabrication of semiconductor devices may be inadequate to process inkless partial wafers same as full inkless wafers. Many partial wafer processing techniques may require additional, specialized hardware, and/or software for the assembly equipment used. Thus, the specialized solution may not be easily implementable and transportable across multiple vendors or contractors performing the partial wafer processing.